发明名称 Chipset synchronization arrangement.
摘要 <p>Each chip (11, 12) of a microprocessor chipset is synchronized by an associated controller (400) which adjusts a control signal (202) for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp (507) which compares the output of an internal clock in each chip with a reference system voltage (508).</p>
申请公布号 EP0133359(A2) 申请公布日期 1985.02.20
申请号 EP19840305107 申请日期 1984.07.27
申请人 AT&T CORP. 发明人 SHOJI, MASAKAZU
分类号 H03K5/13;G06F1/10;G06F13/42;(IPC1-7):G06F1/04 主分类号 H03K5/13
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