| 摘要 |
PURPOSE:To obtain a static RAM circuit of complete CMOS which is excellent in both area and performance by a construction wherein the high-load wirings are shared by the low-resistance metal wirings by using a multilayer metal wiring process. CONSTITUTION:Metal wirings are constructed on the condition of the use of a CMOS process in which two layers can be utilized, the upper layer metal wiring being used for data lines 28 and grounding lines 29, 29', and the lower layer metal wiring being used for word lines 27 and a power supply line 32 that are othogonal thereto. This is because the connection with the low layer metal wiring can easily become smaller in area because of the connection of the word line polysilicon wirings and the metal wirings, and speeding up is intended by using the upper layer wiring having the least delay time as the data lines. The construction is such that the left and right sides of a memory cell are separated by the grounding lines in order to prevent the unit data line pair from adversely affecting other bits. |
