| 摘要 |
PURPOSE:To reduce an area of one transistor memory cell and also to extend a storage time by arranging a capacity part on the top of a mesa domain through providing a dielectric layer of different kind and a transistor part on the area longitudinal to the mesa domain. CONSTITUTION:An n<+>-layer 2 is formed on a p-type Si 1, which is covered with an n-epitaxial layer 3, an SiO2 4 and an Si3N4 5 are formed selectively opposite to the layer 2, and the layer 3 is etched. The layer 3 is oxidized 6 with the film 5 as a mask, and the surface is made almost equal to the top of a mesa domain 3a. The film 5 is removed, ion is implanted, and the layer 3a is isolated into layers 8, 9 with a p-layer 7. An Al 10 is metallized, and an etched groove is formed on the film 6 from under a canopy top of the film 4. Next, the film 4 and the Al 10 are removed, a gate oxidized film 11 is provided, Si3N4 12 and poly-Si 13 are built up selectively on an oxidized film 11a on the surface of the mesa domain, which are covered with SiO2 14, and an Al wiring 15 is formed. According to this constitution, an occupied area is sharply decreased, a cell capacity is increased, and thus a storage time is extended. In addition, a parasitic capacity is small, and a high speed operation can be expected. |
