| 摘要 |
PURPOSE:To attain the clock step operation of the whole system by providing the system with a means uniforming the phase of clocks to be supplied to a data processor. CONSTITUTION:Outputs from oscillators 1, 10 are supplied to FFs 2, 11 and a clock start/stop control circuit 14. When clock stop is specified by a signal 22, the control circuit 14 stops the FFs 2, 11. When in-phase clocks are specified by a signal line 23, a signal line 25 commands switching circuits 6, 7 so that the outputs of delay lines 12, 13 are outputted to respective signal lines 8, 9. A clock stop signal 24 is controlled so that one clock is generated to the signal lines 8, 9 in the clock stop state. |
