发明名称 MEMORIA MORTA INTEGRATA
摘要 An integrated circuit programmable read only memory is arranged in a matrix having a plurality of memory cells arranged in rows and columns. A particular cell in a matrix is addressed by selecting the appropriate row and column. A destructible memory element connects a column to a row at each intersection. The currents for programming adjacent memory cells corresponding to a row of the memory are diverted by a single path.
申请公布号 IT1064203(B) 申请公布日期 1985.02.18
申请号 IT19760029326 申请日期 1976.11.15
申请人 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL 发明人
分类号 G11C17/00;G11C5/06;G11C17/08;G11C17/16;H01L21/8229;H01L23/525;H01L27/102;(IPC1-7):G11C/ 主分类号 G11C17/00
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