发明名称 MIS TYPE SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To accomplish the reduction of inter-element dimensions and the increase of the capacitance of a charge accumulated section at the same time by a method wherein grooves are formed in a semiconductor substrate, which are used as the insulation among the capacitance sections of a memory cell, and further the side surface section of the groove is utilized as the capacitor. CONSTITUTION:The grooves 20 are formed in the semiconductor substrate corresponding to the insulation region among the capacitance sections adjacent to each other of a memory device having one insulation gate type FET and the capacitor provided adjacent thereto on a semiconductor substrate as the unit of information. An impurity layer of the same conductivity type as the semiconductor substrate and higher concentration than the substrate is formed in the substrate at the bottom of this groove. An insulation film is formed in the grooves and on the surface of the substrate corresponding to the capacitance sections 21, and a conductive substance is deposited in the grooves and on the insulation film at the capacitance sections, being thus constructed as the capacitance electrode of the memory device. In this manner, the formation of the inversion layer on the groove side surface is enabled by diffusion of the impurity of reverse conductivity type to that of the substrate into the groove side surface, resulting in contribution to the increase of capacitance.
申请公布号 JPS6031268(A) 申请公布日期 1985.02.18
申请号 JP19830139007 申请日期 1983.07.29
申请人 NIPPON DENKI KK 发明人 NAKAMURA KUNIO
分类号 H01L27/10;H01L21/8242;H01L27/108;H01L29/78 主分类号 H01L27/10
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