发明名称 MULTIPLEX CIRCUIT
摘要 PURPOSE:To obtain an excellent output signal by providing a control means for controlling plural multiplex means applying multiplexing to each signal of different channel number and plural multiplex means in common and for leading out selectively an output from any multiplex means to decrease the waveform distortion of the signal to be processed. CONSTITUTION:The output side of filters A, B connected in parallel with channels 1-8 of the input terminal in common is connected to a multiplexer 20 provided newly and a multiplexer 5 respectively. A clock control circuit 9 controls the multiplexer 5 and the multiplexer 20 provided newly. In this circuit, the multiplexers 20 and 5 are controlled to be in ON-and OFF-state respectively in the 8-channel mode. In the 32-channel mode conversely, the multiplexer 20 is in OFF-state and the multiplexer 5 is in ON-state. The control is attained by the clock control circuit 9 in any case.
申请公布号 JPS6031331(A) 申请公布日期 1985.02.18
申请号 JP19830140291 申请日期 1983.07.29
申请人 MITSUBISHI DENKI KK 发明人 CHIBA KAZUHIRO
分类号 H04J3/04;H03K17/00;H04J3/10 主分类号 H04J3/04
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