发明名称 ANALYSIS PROCESSOR FOR PLURAL PATTERNS
摘要 PURPOSE:To easily analyze the complicate connection state of islands and sea by making a scan vertically and horizontally while regarding the background as the sea and patterns as islands and obtaining a binary-coded output, extracting a succession of logic ''1'' and the surrounding state of logic ''0'', and further inverting logical values. CONSTITUTION:A screen 11 to be processed is shot by a camera 12 while the sea, islands, and lakes are denoted as S, I, and L, and a binary coding circuit 13 outputs ''1'' and ''0''. Those binary-coded signals are processed by extracting circuits 15-17 for island segment information, island connection couple information, and island surrounding couple information, and their outputs are inputted to an island image information memory 18. The binary-coded signals are inverted 14, and sea segment information, sea connection couple information, and island surrounding couple information are extracted 19-21 to store sea image information in a memory 22. Various pieces of information on the islands and sea are supplied to a processor 23 through a system bus 27 to perform processing such as an analysis of connectivity and removal of duplicate information according to a program in an ROM24; and the islands and sea are given numbers respectively and stored in an RAM25, and arithmetic is carried out to obtain an output from an interface 26. Thus, an analysis of a complicate pattern and the detection of a fault are facilitated.
申请公布号 JPS6029871(A) 申请公布日期 1985.02.15
申请号 JP19830127798 申请日期 1983.07.15
申请人 FUJI DENKI SEIZO KK 发明人 HONGOU YASUO
分类号 G06T7/60;G06T7/00 主分类号 G06T7/60
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