| 摘要 |
PURPOSE:To reduce the time of initialization when a power supply is applied by producing an exclusive OR signal with input of a parity bit and a specific bit of an address to store the OR signal to a memory and then supplying said OR signal to be read out and the specific bit to produce a parity bit. CONSTITUTION:It is defined that a specific bit (an) of an address selects a memory cell within a memory cell group A or B when the logic value is set at ''0'' or ''1'' respectively. A parity bit (dp) is supplied to an exclusive OR gate G1 together the bit (an). The gate G1 produces an exclusive OR signal (dp') to store it to a unit memory MP. At the same time, the gate G1 produces the bit (dp) from the signal (dp') to be read out and the bit (an) and transmits the bit (dp) to a parity circuit PC. Therefore it is regarded that data bits d0-d3 which are logically normal when viewed from the circuit PC and the bit (dp) are supplied to unit memories MO-M3 and MP respectively when the power supply is cut off. Therefore no initialization is needed even when the power supply is applied. |
