| 摘要 |
PURPOSE:To obtain memory cell structure for a high integrated high speed ROM by a method wherein word lines are arranged in the linear type, first layer grounding conductors are arranged in parallel with the word lines, and second layer data lines are arranged as to make a right angle with the word lines. CONSTITUTION:Word lines 9 formed by using doped poly-silicon, or a metal of small resistivity are arranged linearly. First layer grounding wirings 10 consisting of aluminum are provided alternately at the gaps of word line arrangement and in parallel with the word lines 9 thereof, and connected to n<+> type diffusion layers 14' through contact holes 23. The diffusion layers 14' are used as the source regions of MOS transistors constructing memory cells. While, data lines 11 are formed of second layer aluminum layers, connected to first layer pads 13 consisting of aluminum through contact holes 24, and the pads 13 are connected to n<+> type diffusion layers 14 through contact holes 25. The diffusion layers 14 are used as the common drain regions of two MOS transistors. |
