| 摘要 |
PURPOSE:To preclude the necessity of the recognition of number of bits per one character and length of stop bits, even for a signals of start-stop synchronism, by providing one clock oscillator in a loop transmission system and making transmission/reception of a synchronous data through the use of clocks. CONSTITUTION:A clock signal is given on a loop transmission line 10 from a station S at all times, a transmission station A frequency-divides this clock signal at frequency dividers 19, 20, is applied to an input section 8 as a sampling signal, samples an input data 4, sets this sample data to a data register 17 and an initial value 1 to a count register 18. If the next sample data is in the same state as before, the count register 18 is incremented by +1. A frame assembling section 15 assembles the data octet formed from the content of the data register 17 and the count register 18 in frame unit, and transmits it to a reception station B via the loop transmission line 10. The reception station B makes inverse operation to obtain an output data 5. |
