| 摘要 |
PURPOSE:To suppress DC level fluctuation by counting down a correction value from a storage value when an output of the 1st comparator circuit is the 1st comparator output and counting up the correcting value to the storage value when an output of the 2nd comparator circuit is the 2nd comparator output. CONSTITUTION:An analog frequency modulating wave is inputted from an input terminal 5, a digitally processed demodulation signal and an output signal from a counter 10 are added (18) and a correction demodulation signal F is outputted. Further, a comparator circuit 19 outputting the 1st and 2nd comparison outputs depending that the signal F is larger than or below the upper limited value X0+alpha, and a comparator circuit 20 outputting the 1st and 2nd comparison outputs depending that the signal F is equal to or over the lower limit value X0+beta or smaller, are provided. When the comparator output of the circuit 19 is the 1st comparison output, a prescribed correction value C is counted down from a stored value X and outputted and when the output of the circuit 20 is the 2nd comparator output, the prescribed value C is counted up to the storage value X and outputted. |
