| 摘要 |
PURPOSE:To attain high speed A/D conversion by sampling and holding an input data dividedly at plural sample holding circuits, applying A/D conversion and then synthesizing the data. CONSTITUTION:An analog signal inputted from an input terminal 22 is sampled sequentially in the N-set of separate timing by the N-set of sample holding circuits SH1, SH2... and held for N times the sampling time. The N-set of A/D converting circuits AD1, AD2-ADN receive the data, they conduct A/D conversion with a time N times the sampling time and the result is outputted sequentially with the separate timing. The data outputted are synthesized by a data synthesis circuit 20, the result is outputted from an output terminal 23 and the operation above is controlled by a control circuit 21. |
