| 摘要 |
PURPOSE:To obtain an invariably synchronized dual calendar mechanism high in reliability by inputting and outputting calendar data from either calendar mechanism to and from a CPU, and providing individually a clock which drives the both in common. CONSTITUTION:A calendar mechanism 6 is used in common for both an in-use and a spare mechanisms, and exactly the same mechanism 7 is provided. A clock generating circuit 6 while sending a clock to a calendar circuit 62 through a clock switching gate 67 sends the clock to the spare mechanism with an output 101. If the mechanism 6 goes wrong, a fault detecting circuit 63 sends a fault signal 105, and a calendar switching circuit 66 sends a calendar switching signal 100 to the stand-by mechanism 7 and also sends a signal 102 to a bus interface INF61 to cut off the calendar data. Once receiving the signal 100, the spare mechanism 7 sends a clock signal from the clock generating circuit which is invariably in operation to its own calendar mechanism and also sends the signal to the bus interface to send out the calendar data to a bus. Thus, high reliability is obtained. |
