| 摘要 |
PURPOSE:To attain a large memory capacity with high-speed operation and small power consumption by constituting a memory cell with a latch circuit and using a differential bipolar FET to a sense amplifier. CONSTITUTION:The memory cell MC consists of memory MOSFETQ1 and Q2 where a gate and a drain are formed alternately into a latch form and high resistances R1 and R2 made of polysilicon layers. While a sense amplifier consists of differential bipolar transistors TRT5 and T6. Then the memory cell reading voltages emerging at common data lines CD and -CD are supplied to the bases of the TRT5 and T6. The collector outputs of the TRT5 and T6 are transmitted to a data output buffer DOB through emitter follower TRT7 and T8. |
