| 摘要 |
PURPOSE:To generate stably various synchronizing signals by combining a horizontal period counter, a vertical period counter, each decoder and a flip-flop circuit controlled by AND of each decoder and also constituting programmable counters and decoders. CONSTITUTION:When a synthesis video signal is inputted from an input terminal 1, a separating synchronizing signal is outputted from a synchronizing separator circuit 2. A vertical pulse and an equalizing pulse in the signal are eliminated from the signal at a 3/4H multivibrator triggered at the leading edge phase at a pulse separation circuit 3, a horizontal period pulse is formed and the pulse is fed to a clock oscillator 4 and a gate circuit 5. On the other hand, the vertical synchronizing pulse is obtained by latching the synchronizing signal at a trailing edge phase of the output signal of the 3/4H multivibrator, and the vertical period pulse is obtained again by latching the vertical period pulse with the horizontal period pulse. The vertical period pulse obtained from the two kinds of pulses through AND is fed to a gate circuit 6. |
