发明名称 DIGITAL RADIO DECODING CIRCUIT
摘要 PURPOSE:To eliminate the need for offset countermeasure by utilizing a 2-bit integration circuit so as to use a value at the 1st bit as a discrimination belt. CONSTITUTION:An integration circuit 12 applies 2-bit integration to a detection waveform through a low pass filter 11. A signal is given to a sample-and-hold circuit 14 at the point of time of 1-bit integration in the process to hold the level at that time. A comparator 18 as a discrimination circuit discriminates whether the level at 2-bit integration is upper or lower than the hold value and outputs '1' or '0' as a result. Since the level at 2-bit integration is discriminated by the level at 1-bit integration, no discrimination level generator is required and the discrimination level is added automatically.
申请公布号 JPS61273050(A) 申请公布日期 1986.12.03
申请号 JP19850114706 申请日期 1985.05.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KIKUCHI TAKESHI
分类号 H04L25/03;H04L25/06;H04L27/00 主分类号 H04L25/03
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