| 摘要 |
<p>Transceivers interface between a multiple access bus and user devices, for transferring variable length data packets between the devices. Each transceiver buffers only one byte of data at a time while sending or receiving a packet. A general purpose computer in the device performs various functions ancillary to byte transfers. Data signals on the bus are in bit-serial asynchronous baseband form. Each byte group of bit signals is preceded by a pair of stop and start signals whose transition forms a time reference for reception of those bits. The timing of the stop signals is tailored to operating characteristics of the device computers and their assigned ancillary functions. Access controls in each transceiver start a timeout sequence when the signal on the bus changes to the stop level and and reset when the level reverses to the start level. If the times level persists longer than the time allotted for transmitting one start-stop pair and a data byte, the timer activates a "bus available" indication enabling the respective receiver and user device to begin sending a packet if ready to do so. New activity on the bus causes the bus available indication to be reset and an interruption to be represented to the user computer. The computer reacts by conditioning the device and adapter to either receive or ignore the incoming packet, depending on destination information in the packet header. The timer threshold can be varied to adapt user devices to various modes of multiple access operation. </p> |
