| 摘要 |
PURPOSE:To increase a signal processing speed by refreshing the contents of a memory while a processor is addressing excepting the memory. CONSTITUTION:Clocks CLK are successively supplied to a processor 11, and the address signal is delivered to a decoder part 15. A period during which the output signals of decoders 15a and 15b are kept at low levels is used for an enable or refresh signal. Then an ROM12, an input/output circuit 14 and other necessary circuits become enable in a period during which the output signal of the decoder 15b is kept at a low level. At the same time, a DRAM13 is refreshed by the output signal of a decoder 15a. |
