发明名称 |
CLOCK SYNCHRONIZING METHOD |
摘要 |
PURPOSE:To digitize a phase comparator easily by using a Doppler frequency between a low frequency reference station and a slave station for the phase comparing frequency of a clock phase lock system in the reference station. CONSTITUTION:The output frequency (f) of a voltage control oscillator 28 in the reference station 200 is repeated through a satelite 20. The slave station 201 receives the repeated frequency (f) as frequency f+fd by Doppler shift and outputs the frequency f+fd from a voltage control oscillator 35. The output f+ fd is repeated by the satellite 20 and received by the reference station as frequency f+2fd. Said received frequency is multiplied by the oscillation frequency fo of a master clock oscillator 21 by a multiplier 22 and its low frequency component f+2fd-fo is extracted by an LPF23. The low frequency component is multiplied 25 by the outputs of the oscillators 28, 21 and the multiplied result is compared with the frequency fo-f obtained through an LPF24 by a phase comparator 26 and the oscillator 28 is controlled by a signal obtained by passing the compared output through a loop filter 27. During the clock phase lock system holds the synchronization, the reproducing clock frequency of the slave station 201 equals to fo. |
申请公布号 |
JPS6027239(A) |
申请公布日期 |
1985.02.12 |
申请号 |
JP19830134348 |
申请日期 |
1983.07.25 |
申请人 |
NIPPON DENSHIN DENWA KOSHA |
发明人 |
KAZAMA HIROSHI;MORIKURA MASAHIRO;UMEHIRA MASAHIRO |
分类号 |
H04B7/15;H04B7/212;H04L7/00 |
主分类号 |
H04B7/15 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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