| 摘要 |
PURPOSE:To provide advantageous circuit integration to the device by inverting a data on a display memory at input/output, writing logical ''1'' at erasing and generating data by means of resistors only to simplify the circuit. CONSTITUTION:In erasing content of the display memory 4, an erase instruction signal SE is applied from a CPU to erasing period generating circuit 10 and the circuit 10 applies an erasing pulse PE to a control circuit 9. A write signal is applied to the memory 4 from a termianl WE' of the circuit 9 during the period of the pulse PE to attain write state. Further, an address signal DISAD is applied to an address terminal A of the memory 4 from an output terminal Y of an address selector 1. Moreover, an output terminal Y' of a bus drive 5 is brought into the high impedance state during this period. Since each line of the data bus 6 is connected to a power supply +B via a resistor 8, a data of logical ''1'' is written in the memory 4 during this period based on the signal DISAD. Thus, this state is apparently the same as erasure of content of the memory 4.
|
