| 摘要 |
PURPOSE:To enable a computer to perform the automatic error recovery processing and to continue the operations of the computer by detecting the error data before it is delivered to a device to be controlled. CONSTITUTION:A parity error detecting circuit 10i detects a parity error at a time point when the output D1i of a latch 9i detects the data on an address M+1 by a clock signal T2a. In such a case, the output Pi is set at H and therefore a delay clock signal T1b is not sent to a latch 9'i. The value of an address counter 7i is not replaced either, and a clock generating circuit 6 stops the output of the clock signal. Therefore the data on a control target value pattern is fixed at the data obtained in a step preceding state where the parity error is detected. While an interruption signal is sent to a computer 1 and an error recovery program is started when an error is detected with a memory module 3i. Then the operations of a computer is started again when the recovery processing is over. |
