发明名称 WIRING METHOD OF INTEGRATED CIRCUIT
摘要 PURPOSE:To increase the density of wirings by previously forming wiring patterns having conductivity among each layer in an insulating film, removing a desired section through etching and forming an electrode or the wiring to an exposed side wall. CONSTITUTION:A CVD oxide film 34, polycrystalline silicon 33 and a silicon oxide film 32 on the surface of an N type silicon substrate 31 are etched so as to have vertical side walls, and N type diffusion layers are formed through the implantation of arsenic ions, and used as sources 35. Thermal oxide films 36 are formed on the surfaces of the exposed substrates, polycrystalline silicon 37 having N type conductivity is deposited, and gate oxide films 38 are shaped. Regions deposited in parallel with the surfaces of the substrates are removed through etching while leaving only gate electrode polycrystalline silicon 37 and the gate oxide films 38 on the side walls of the insulating films through etching in the vertical direction. Epitaxial films 39 are formed selectively only on the exposed single crystal silicon substrates. A channel region 40 and a drain region 41 are each formed through ion implantation.
申请公布号 JPS6025254(A) 申请公布日期 1985.02.08
申请号 JP19830133329 申请日期 1983.07.21
申请人 NIPPON DENKI KK 发明人 ENDOU NOBUHIRO
分类号 H01L21/28;H01L21/3205;H01L21/768;H01L23/522;H01L29/78 主分类号 H01L21/28
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