发明名称 TIME DIVISION MULTIPLEX CHANNEL SWITCH CONTROLLER
摘要 PURPOSE:To attain one switch control with a half of buffer memories by conducting twice the reading of buffer memories storing information subject to time division multiplex in the unit time. CONSTITUTION:Two buffer memories 1, 2 store a signal subject to time division multiplex and selectors 3, 4, 5 and 6 select the output and give an output to a time division multiplex line. An output highway time slot selecting signal is written in switch memories 7, 8, 9 and 10 so as to control the write/read of the buffer memories 1, 2. A time slot address signal gives an output highway time slot designation signal to the buffer memory 1 as a read address and gives a designated signal to the selectors 3, 4. The same operation is conducted to the buffer memory 2 at the same time.
申请公布号 JPS6025398(A) 申请公布日期 1985.02.08
申请号 JP19830133980 申请日期 1983.07.21
申请人 NIPPON DENKI KK 发明人 MATSUSHITA HIDEAKI
分类号 H04Q11/04;(IPC1-7):H04Q11/04 主分类号 H04Q11/04
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