| 摘要 |
PURPOSE:To provide a sense circuit allowing a high speed and high sensitive sense operation by arranging the circuit connecting current mirror type sense circuits in two stage in vertical sequence. CONSTITUTION:In the wrong most condition such as a CMOS semiconductor memory that a BL potential V2 is lowering, while a potential V1 of a bit line BL' is constant at a Vcc level (5V), a potential V3 at a connecting point A of an intermediate potential between a power supply voltage Vcc (5V) and a ground potential GND (0V). On the other hand, a potential V4 at the connecting point B rises because the potential V2 of the bit line BL is reversely amplified. MOS transistors Q6 and Q7 are continuity-controlled on the basis of the potentials V3 and V4 at the connecting points A and B to perform a sense operation. A high speed and high sensitivity sense operation is possible because of being able to obtain a comparison output by amplifying this potential in the second phase circuit, before setting the potentials V3 and V4 at a sufficient high level or low level. |
