发明名称 TIMER UPDATING SYSTEM OF ELECTRONIC COMPUTER
摘要 <p>PURPOSE:To execute easily and delicately a diagnosis of a timer by making an external clock ineffective by an ineffective instruction by a microprogram, and counting up a real timer by a count instruction. CONSTITUTION:A count instruction frequency (n) is stored in an address A of a memory 4, and subsequently, the contents of the address A are shifted to an address D. Next, an ineffective instruction 8 for making a one millisecond external clock 5 ineffective is given to an FF10, and a real time timer 1 is stopped. An output of the timer 1 of this time point is stored in an address B, and thereafter, a count instruction 9 is given to a timing circuit 6 through an OR circuit 12, and the circuit 6 outputs a count pulse 7 and counts up the timer 1. On the other hand, whenever the instruction 9 is outputted, the contents of the address A are subtracted by ''1'', compared with ''0'', and when they become ''0'', an output of the timer 1 is stored in an address C. Thereafter, a value derived by adding the contents of the address D to the contents of the address B is compared with the contents of the address C, and in case when they coincide with each other, it is decided that the timer 1 is executing normally an updating operation.</p>
申请公布号 JPS6024616(A) 申请公布日期 1985.02.07
申请号 JP19830130972 申请日期 1983.07.20
申请人 NIPPON DENKI KK 发明人 IKEGAMI YOSHIROU
分类号 G06F9/48;G06F1/04;G06F1/14;G06F9/46 主分类号 G06F9/48
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