| 摘要 |
<p>PURPOSE:To obtain an address gate (AG) signal and a pre-charge (PC) signal having the same time interval by the frequency of 1/2 conventional frequency by setting a clock inputted to an odd stage and a clock inputted to an even stage to the opposite phase. CONSTITUTION:A clock B setting a clock E (A in the figure) from a CPU to the opposite phase by an inverter 7 is inputted to the first stage of a six stage shift register. On the other hand, the second clock CP (C in the figure) of a high frequency is supplied to the first, the third and the fifth stages of this shift register, and the second clock CP inverted through an inverter 8 is supplied to the second, the fourth and the sixth shift registers. Accordingly, the output E of the second stage becomes that delaying the output D of the first stage by a time of a half period of the second clock C, the outputs E-I of the third-sixth stages become successively those which are delayed by every half period portion of the second clock C, and an output AG (J in the figure) and an output PC (K in the second figure) are obtained.</p> |
