发明名称 VECTOR PROCESSING DEVICE
摘要 PURPOSE:To read out efficiently a vector data by reducing a wasteful memory overhead, when reading out in multiple the vector data on a main storage by shifting a reference range little by little. CONSTITUTION:A data read-out from a main storage is executed only once of A (1-m+2), and a read-out data distributing circuit distributes a data required for correspondence of each vector register basing on an information such as a head element number, a vector length, etc. For instance, the head element number of the data transferred to vector registers R1, (R1+1)-(R1+3) become 1, 2, 2 and 3, respectively, and the vector length becomes (m). According to such a method, it does not occur that the same element data is overlapped and read out, and an efficient memory access is executed. Also, although a read-out port from the main storage is only one, the data can be stored simultaneously in plural vector registers, threfore, the data required for an arithmetic can be prepared quickly.
申请公布号 JPS6024672(A) 申请公布日期 1985.02.07
申请号 JP19830130817 申请日期 1983.07.20
申请人 HITACHI SEISAKUSHO KK 发明人 OMODA KOUICHIROU;NAGASHIMA SHIGEO
分类号 G06F17/16;G06F15/78;(IPC1-7):G06F15/347 主分类号 G06F17/16
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