| 摘要 |
PURPOSE:To cause no multiple operation by executing mutually an interlocking between each input/output control electronics CE, and preventing a simultaneous operation of the CE, in case of an abnormality has occured in a decoding circuit, etc. of an address bus. CONSTITUTION:An address signal, a data signal and a control signal outputted from a processor 1 are inputted to a selection controlling circuit 10, a buffer 9 and an I/O controlling circuit 8, respectively. Also, the control signal is inputted to the buffer 9 and the circuit 10 through the circuit 8, and informs that the control of this time is ''input'' or ''output''. Also, a non-operating signal from other CE is inputted to the circuit 10, by which a selecting signal is outputted to a driving circuit 11. The circuit 11 outputs a control signal to a corresponding input/output circuit among input/output circuits 3-1-3-1-m by the data signal and the selecting signal. In this way, it is possible to cause no multiple operation, by preventing a simultaneous operation of the CE. |
