发明名称 AGC SYSTEM
摘要 PURPOSE:To receive a bust signal without error by controlling the gain through the utilization of the content of storage of a memory storing sequentially an AGC output voltage with revision while a signal is inputted and controlling the gain depending on the storage content immediatly before the interruption of signal when the signal is interrupted. CONSTITUTION:When an output of a peak-to-peak value detector 7 is reference voltage (b) or over, a comparator 9 revises the content of the memory 8 into a digitized value of a compared output between the output of the peak-to-peak value detector 7 and a reference voltage (a), and the stored content revised in this way is used as a control value of a gain variable amplifier 2 and a bias voltage value of an Avalanche photodiode 1. At the interruption of signal, an output of an AGC circuit 4' is lower than the reference voltage (b) and the comparator 9 outputs a signal inhibiting the revision of the stored content of a memory 8. Since the stored content of the memory 8 is kept to a value just before the signal interruption, the bias voltage of the Avalanche photodiode 1 and the control voltage of the gain variable amplifier 2 are fixed to the value just before the signal interruption.
申请公布号 JPS6022816(A) 申请公布日期 1985.02.05
申请号 JP19830131617 申请日期 1983.07.19
申请人 FUJITSU KK 发明人 YAMANE KAZUO
分类号 H04B10/572;H03G3/00;H03G3/20;H04B3/04;H04B10/00;H04B10/07;H04B10/293;H04B10/564 主分类号 H04B10/572
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