发明名称 DIGITAL SIGNAL MODULATING AND DEMODULATING SYSTEM
摘要 PURPOSE:To decrease the effect of waveform deterioration by applying 2-bit summed up quantity conversion to a signal at a transmission side, and appling the GMSK (Gaussian-filtered Minimum Shift Keying) modulation thereto, transmitting it and allowing the reception side to apply the detected signal with full wave rectification to identify sequentially the integration value between two time slots. CONSTITUTION:An input signal is transmitted through the summed up quantity conversion circuit comprising an exclusive OR circuit 12 and a delay circuit 14 having a delay time of 2T (T is input signal time slot) and through a GMSK modulation circuit 13. The signal is detected by a detection circuit 22 at the reception side and a base band signal is led to a full-wave rectification circuit 23. An output of the rectifier circuit 23 is inputted to integration circuits 24, 25 for 2T period where the integration period is shifted by one time slot period T. The output of the integration circuits 24, 25 is identified by identification circuits 28, 29 at the end of period of integration and outputted to an output terminal 31 through a selection circuit 30.
申请公布号 JPS6022854(A) 申请公布日期 1985.02.05
申请号 JP19830131399 申请日期 1983.07.18
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 OGOSE SHIGEAKI;TANAKA KIYOSHI
分类号 H04L25/497;H04L27/10;H04L27/20;H04L27/233 主分类号 H04L25/497
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