| 摘要 |
Monolithically integrated semiconductor memory with a matrix of identical storage cells arranged rows and columns in the form of a coordinated MOS field-effect transistors and storage capacitors in the form of an MOS capacitor and wherein, also, a comparator and a comparison cell is formed of one of the storage cells are associated with each matrix column, including a method for bridging over a point of interruption in a course of a bit line extending from one to another of at least two adjacent storage cells of at least one column. The bridging method may be an MOS field-effect transistor having a current-carrying path over which the point of interruption is bridged.
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