| 摘要 |
A data error correction circuit is provided, which receives input data having check bit data added thereto, the input data being divided by a generator polynomial G(x) in terms of the modulo 2 and multiplied by a correction polynomial M(x) in terms of modulo 2. An error in the input data is detected and corrected in accordance with contents of a syndrome obtained by these operations. The data error correction circuit includes a latch circuit and a presettable data input circuit. Data from the presettable data input circuit is divided by the generator polynomial G(x) in terms of the modulo 2, and remainder bit data obtained thereby is stored in the latch circuit as the correction polynomial M(x).
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