| 摘要 |
<p>PURPOSE:To relieve the load on a processor relating to the counting of the number of data and to attain high speed memory accessing by providing a data counter to the buffer memory in a packet communication device. CONSTITUTION:When a write start signal WST is inputted, an address counter 2 is cleared. When a write request signal WQ is incoming succeedingly, a data on a data bus 6 is fetched to a storage position of a memory matrix 1 indicated by the counter 2, the counter 2 is advanced stepwise and a memory enable signal ME is transmitted during the time to reject accessing. When a read start signal RST is inputted at the transition from write to read, after the counter 2 transfers the value to an address register 3, the counted value is cleared. When the signal RST is fed again at the read state, the register 3 is not set. When a read request signal RQ exists afterward, a data in the memory 1 represented by the counter 2 is feteched to a bus 6 to increase the counter 2, and when the value of the counter 2 is larger than the value of the register 3, a collation circuit 4 transmits a read completion RF.</p> |
