| 摘要 |
<p>PURPOSE:To attain a high speed operation and less power consumption by forming high frequency signals through frequency multiplication of the output signals in the oscillation circuit which forms reference time signals to select the reference signals and the multiplied signals according to the information processing mode. CONSTITUTION:A frequency multiplier-N is constituted of a PLL circuit: Reference time signals (about 32KHz) formed by the oscillation circuit OSC are supplied to one of the inputs in a phase comparator PD. In the other input in the circuit PD, the oscillation output in a voltage controlling oscillation circuit VCO is divided by 1/2<n>, and inputted. The output in the circuit PD is changed into LPF, also into direct current and into control signals of the oscillation circuit VOC. The circuit PD forms and locks the phase comparison output so that the frequency of both input/output signals may conform to each other. When the circuit PD is set at n=7, the circuit is locked at about 4MHz. Then both low/high frequency is inputted in the multiplexer MPX, and is selected according to the information processing mode, thereby making a high speed processing and less power consumption possible.</p> |
