发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To accelerate the operation of a bipolar transistor in MOS and bipolar integrated circuit by a method wherein the impurity concentration in an external base region is increased more than that in a true base region with base resistance reduced while the relative junction depth of the external base region is decreased to reduce the paracitic capacity. CONSTITUTION:A P type diffusion layer 7a to be an external base region is formed on an N<-> type epitaxial layer 4 excluding an oxide film 5 and the lower part of another film 12. Next the emitter part of the oxide film 12 is removed by directional dry etching process using a film 11 as a mask. Then a P<-> type diffusion layer 7b to be a true base region is formed by thermal diffusion of P type impurity from the hole made by removing the film 12 while N type impurity is thermally diffused from the same hole to form an N<+> type diffusion layer 8 to be an emitter region on the P<-> type diffusion layer 7b. Through these procedures, the P<-> type layer 76 may be formed separately from the P type diffusion layer 7a to be the external base region outside said diffusion layer 7b to increase the impurity concentration in the external base region 7a more than that in the region 7b. Consequently, the resistance in the region 7a in a bipolar transistor may be reduced to accelerate the operation of said transistor comparing with the case of uniform impurity concentration base region.
申请公布号 JPS6020570(A) 申请公布日期 1985.02.01
申请号 JP19830127643 申请日期 1983.07.15
申请人 HITACHI SEISAKUSHO KK 发明人 WATANABE KUNIHIKO;OKADA DAISUKE;HARA SHIYOUJI
分类号 H01L29/73;H01L21/331;H01L29/72;H01L29/732;(IPC1-7):H01L29/72 主分类号 H01L29/73
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