| 摘要 |
<p>PURPOSE:To simplify the circuit by generating plural timings from the basic timing, selecting a specific timing among them, and providing a circuit which generates an output signal by operating a logic arithmetic in the input signal with this said signal. CONSTITUTION:A input signal 4 is processed by the timings 8-10 in logic circuits 1-3, and outputted 7. The timings 8 is inputted from outside, receives a specified delay from delay circuits 22-29, and generates timings 32-39. For a delay time of each circuit, circuits 22-25 as well as 26-29 are decided for timings 9 and 10 so that either one of timings 32-35 or one of timings 36-39 may be fitted for the allowable error of timings 9 and 10. A test select circuit 40 outputs 42 by selecting one of the generated timings 32-39 by the external signal 41. This output 42 is compared with the timing 8, and the output, which is suitable to the timings 9 and 10, is determined from the timings 32-39. After this test has been completed, the semiconductor board 43 is stored in the case, thereby improving yield and reducing the number of terminals.</p> |
