| 摘要 |
PURPOSE:To contrive to enhance the speed and to enhance the withstand voltage of a drain earthed laterally structural insulated gate field effect transistor by a method wherein a high concentration impurity buried layer is provided in the neighborhood directly under the source thereof as not to reduce the withstand voltage between the source and the drain. CONSTITUTION:An N type buried layer 2A is formed in a high resistivity P type substrate 1A, and after N type epitaxial layers 3A-3C are formed, P type diffusion layers 4A, 4B to be used for element isolation and as the drain of a laterally structural MOSFET are formed. After then, formation of a gate oxide film 101, formation of a poly-Si gate 7A, ion implantation for formation of a P type impurity diffusion layer 5A to enhance the withstand voltage, formation of a P type diffusion layer 8A, formation of an N type diffusion layer 9A to short-circuit between the epitaxial layer and the source, formation of contacts, and formation of Al wirings are performed according to the manufacturing method of the usual high withstand voltage laterally structural MOSFET. Accordingly, because the high concentration impurity buried layer 2A is existing in the neighborhood directly under the source diffusion layer 8A, a punch through is hard to be generated between the source and the drain (the substrate), and the effect of a vertically parasitic PNP transistor can be reduced, too. |
