发明名称 NOR CIRCUIT
摘要 PURPOSE:To vary the speed of the circuit operation by bringing a signal inputted to an N-channel MOS gate of the NOR logic into an L level in precharging an output line. CONSTITUTION:The 1st stage NOR logic consists of N-channel MOSes 33, 34 and 35. The input of this logic is an output 26 of a driver comprising P-channel MOSes 30, 15 and an N-channel MOS 16 and an output is a potential at a terminal 17. The P-channel MOS 13 is utilized for precharging an output terminal. When inputs 26 or the like to the NOR logic are all at L level, since the N-channel MOSes 33-35 are turned off, the output 17 is not grounded and a precharged electric charge is not discharged, then the level is kept to H level. When any one input goes to H, the output 17 is grounded and the output is transited to the L lveel. The next stage NOR logic consists of N-channel MOSes 37-39. A clock signal line 25 designates a precharge period.
申请公布号 JPS6020632(A) 申请公布日期 1985.02.01
申请号 JP19830127717 申请日期 1983.07.15
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 NOGUCHI YOSHIKI;HAGIWARA YOSHIMUNE;NAKAMURA HIDEO;MASUDA HIROYUKI
分类号 H03K19/096;H03K19/20 主分类号 H03K19/096
代理机构 代理人
主权项
地址