发明名称 DATA MODULATOR-DEMODULATOR
摘要 PURPOSE:To reduce the processing time by adding/subtracting a real part and an imaginary part of each vector before multiplication so as to conduct a complex number of operation through three times of multiplication. CONSTITUTION:A real part alpha and an imaginary part of a multiplicand (a) are inputted to terminals 1, 2 a real part gamma and an imaginary part delta of a multiplier (b) are inputted to terminals 3, 4 and after (alpha-beta) and (gamma+delta) are calculated respectively at adding/subtracting devices 5, 6, the operation of m1=(alpha-beta)X (gamma+delta) is executed at a multiplier 7. As to the output of the imaginary part of the complex number operation, the operation of m2=alphaXdelta amd m3=betaXgamma is conducted by multiliers 8, 9, the results are added by an adder 12 and outputted to a terminal 14. As to the real part, the result of multiplication m2, m3 utilized for the output of the imaginary output and the output m1 of the multiplier 7 are used and the operation of m1-m2+m3 is conducted by an adding/subtracting devices 10, 11. The result is (alpha-beta)X(gamma+delta)-alphadelta+betagamma=alphagamma-betadelta and the result of operation of the real part being target is obtained.
申请公布号 JPS6020666(A) 申请公布日期 1985.02.01
申请号 JP19830128550 申请日期 1983.07.14
申请人 NIPPON DENKI KK 发明人 TATSUI NORITAKA
分类号 H04L27/00;(IPC1-7):H04L27/00 主分类号 H04L27/00
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