| 摘要 |
PURPOSE:To obtain a data having a constant error rate by loading a value of the 2nd counter counting 1/n frequency-division of a clock to the 1st counter counting the clock at data detection and inverting the data by a carry of the 1st counter. CONSTITUTION:A synchronizing clock transmitted from a data transmitter 1 is frequency-divided by 1/n and the result is fed to the 2nd counter 10. When a data IN is detected, the value of the 2nd counter 10 is loaded to the 1st counter 9 to start the count of the synchronizing clock. The 1st counter is a 4-bit counter and transmits a carry every time the counter counts 16, and a data inverting circuit 13 is activated in this case to invert the bit in a serial data at that point of time. Since the 2nd counter 10 is operated freely, a random value is loaded to the 1st counter and the carry produces an error bit to the data, then a digital data having a constant error rate is produced. |
