发明名称 TIMING SYNCHRONOUS CONTROLLER
摘要 <p>PURPOSE:To prevent wastefullness by asynchronism by outputting timing signals from a reference clock pulse to plural devices and comparing the time-up signals with the admission signals from the calculator to stop all the control in case of incompleted conditions. CONSTITUTION:A generalizing controller 11 controls the plant 12 by the reference clock in a timing synchronous controller 13 through each controller 1-N. A signal 01 is inputted from the controller into the synchronous controller 13; when a signal A from the calculator of the generalizing controller 11 is already there, a signal 11 is outputted; a signal T1 is immediately outputted as shown in the figure; the timing signals T2-T4 are outputted in successive delayed order. The signal I1 actuates a timer 201. Even when the timer 201 is time up, but if a generalizing signal B is not yet there, the signal I1' is not outputted; the following sequence is stopped and a signal I2' is outputted. When the signal I2' is outputted, a stop signal 800 is outputted in each controller 1-N, and at the same time stops the controller immediately, thereby allowing prevention of wastefulness of each equipment due to asynchronism.</p>
申请公布号 JPS6020225(A) 申请公布日期 1985.02.01
申请号 JP19830127938 申请日期 1983.07.15
申请人 HITACHI SEISAKUSHO KK 发明人 MORIYAMA KUNIO;IBA DAIZOU;MATSUKI TSUTOMU
分类号 G06F1/06;G06F1/04;G21B1/00;G21B1/11;G21B1/25 主分类号 G06F1/06
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