| 摘要 |
PURPOSE:To prevent migration and to expand signal level margin by connecting a pair of load resistors to both terminals where a wiring resistor of an optional output terminal of wiring constituting a wired logic is maximized to disperse the concentration of a current flowing to the wiring. CONSTITUTION:The wired logic is constituted by connecting selectively an emitter of an inverting output transistor (TR) Q6 or a non-inverting side output TR Q5 of ECL gate circuits G1-Gn comprising TRs Q1-Q6 by means of wiring L. In forming a wired logical gate Gw by the wiring L, two load resistors RL prepared respectively for the emitter of the inverting output TR of the gate G1 and the gate Gn being both the longest ends of the said wiring are connected respectively as series constitution. Thus, the load resistor is connected respectively at two points where the wiring resistance between two points are maximized. |
