| 摘要 |
PURPOSE:To attain the reduction in power consumption and number of circuit constitution by constituting an input and an output register by a delayed flip- flop circuit. CONSTITUTION:The input side register 21 and the output side register 31 are both formed by the delayed flip-flop circuit and an inverted clock signal CK' is applied to a logical gate 11 clipped between the registers. When the inverted clock signal CK' is logical L, P-channel transistors (TRs) 71, 71' and 71'' are turned on and N-channel TRs 72, 72' and 72'' are turned off. Then nodes 81, 81' and an output terminal 81'' go to logical H. When the inverted clock signal CK' goes to logical H, the P-channel TRs 71, 71' and 71'' are turned off and the N- channel TRs 72, 72' and 72'' are turned on, and the nodes 81, 81' and the output terminal 81'' are disconnected from a power supply line and also they go to the logical state specified by the state of TRs 41, 42, 51, 52 and 61. |
