| 摘要 |
<p>A packet switching system in which a remote real-time clock (121) is accurately synchronized to a standard real-time clock (119) via X.25 (CCITT) controlled high-speed transmission links (11). Synchronization is achieved by the transmission of an interrupt packet and a data packet between a remote processor (120) controlling the remote real-time clock and an administrative processor (106) controlling the standard real-time clock. Synchronization involves the following steps: (1) assembling an interrupt packet comprising the least significant bits of the remote real-time clock for transmission to the administrative processor by the remote processor, (2) calculating bits representing the difference between the transmitted least significant bits of the standard real-time clock by the administrative processor, (3) assembling a data packet comprising bits representing the state of the standard real-time clock and the difference bits for transmission to the remote processor by the administrative processor, (4) adding the difference bits to the bits representing the state of the remote real-time clock by the remote processor, and (5) adding a predefined value to the most significant bits of the remote real-time clock by the remote processor of the transmitted least significant bits of the standard real-time clock are numerically greater than the least significant bits of the remote real-time clock.</p> |
