发明名称 ERROR CHECKING SYSTEM OF MULTIPLE GENERATING CIRCUIT
摘要 PURPOSE:To check data as soon as a multiple is generated by applying 1/n multiplication to the data obtained by applying (n) multiplication to the input data given from outside and comparing the 1/n-multiplied data with the input data given from the outside. CONSTITUTION:The output of an n-multiple generating circuit 4, i.e., an (n) multiple of an external input data 1 is supplied to a 1/n-multiple generating circuit 5. Therefore it is decided that the output data of the circuit 4 is correct if the result of comparison of an n-multiple error detecting circuit 8 has coincidence. If no coincidence is obtained, it is possible to detect an error of the output data of the circuit 4. In the same way, the 2nd switch circuit 3 supplies the external input data 1 to the circuit 5 and the output of the circuit 5 is supplied to the circuit 4 through the 1st switch circuit 2. A 1/n-multiple error detecting circuit 7 detects the discordance between the output of the circuit 4 and the data 1 to perform check of errors.
申请公布号 JPS6019239(A) 申请公布日期 1985.01.31
申请号 JP19830126980 申请日期 1983.07.14
申请人 NIPPON DENKI KK 发明人 SUZUKI KEIICHI
分类号 G06F7/38;G06F7/00;G06F7/499;G06F11/00 主分类号 G06F7/38
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