| 摘要 |
<p>PURPOSE:To attain an input even with the N-bit serial or parallel data by altering the circuit constitution of an N-bit shift register so that it can be applied as a latch circuit for N-bit parallel signals. CONSTITUTION:N-bit parallel data input terminals DN-1, DN-2-D0 are provided. A control circuit 5 performs switching for serial and parallel inputs so that the serial data is supplied when an output signal 8 is set at a high level and the parallel data is supplied when an output signal 6 is set at a high level respectively. In other words, the FFs connected in series function as a shift register when the signal 8 is set at a high level. Then the parallel data is supplied from the terminal DN-1, etc. while an input data signal 7 is kept at a high level. While the signals latched by FFs including an FN-1, etc. are transmitted to a microprocessor via a QN-1, etc. Thus an input is possible with both serial and parallel data of N bits by altering the circuit constitution.</p> |
