| 摘要 |
PURPOSE:To obtain a pull-up resistor without lowering the utilization rate of a gate by forming a polycrystalline Si layer between cell blocks and forming a high resistance element and a low resistance element through selective diffusion when the high resistance element and the low resistance element are shaped to a master slice C-MOS semiconductor element. CONSTITUTION:A polycrystalline Si layer is formed in a wiring region between a cell block and a cell block, and low resistance and high resistance elements are formed through a selective diffusion process. These low and high resistance elements are connected properly through a master slice process, and utilized as arbitrary resistance elements. Accordingly, the low resistance polycrystalline Si element 302 and the high resistance element 303 are formed under a wiring region between the cell block 301 and the cell, and these elements are connected in series, thus obtaining a desired pull-up resistor without lowering the utilization rate of a gate. |
