发明名称 CLAMP CIRCUIT
摘要 PURPOSE:To always make a period where the output value of an analog/digital converter is equal to a minimum level constant value by increasing a DC level when the result of applying analog/digital conversion to a waveform of a specific part is smaller than a predetermined value and decreasing the level in other cases by the control. CONSTITUTION:A minimum level detecting circuit 13 brings its output to a high level during a period only when an output value of the analog/digital converting circuit 2 is equal to the minimum level and brings its output to a low level during other periods. Since a diode 14 is conductive during the period of high level, a potential of a capacitor 16 is increased by a time constant decided by a resistor 15 and a capacitor 16, and the DC level of a clamp signal Vc is increased through a resistor 18. Since the diode is nonconductive during the low level, the DC level is descended by the time constant decided mainly by a resistor 17 and the capacitor 16. That is, when the DC level of the Vc is descended, the period o of the output value of the analog/digital converting circuit 2 is equal to the minimum level is made longer.
申请公布号 JPS6019364(A) 申请公布日期 1985.01.31
申请号 JP19830126056 申请日期 1983.07.13
申请人 HITACHI SEISAKUSHO KK 发明人 FUKINUKI NORIHIKO;TAKIZAWA MASAAKI
分类号 H04N5/16;(IPC1-7):H04N5/16 主分类号 H04N5/16
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