| 摘要 |
<p>PURPOSE:To obtain a data processor which attains a low level of power consumption by using two oscillation parts of high and low speeds to use a low- speed clock in case a battery or a capacitor is used for back-up purpose with inhibition of a high-speed operation. CONSTITUTION:One of two clocks generated by the 1st and 2nd oscillation parts 1-2 and 1-4 with different frequencies is switched by a clock control part 1-7 and applied to a central processing part 1-8. The switching of clocks is carried out by applying a detection signal 1-14 given from a detection part 1-6 which detects that the coincidence is obtained twice and continuously between the logic levels of the clocks given from both parts 1-2 and 1-4 and a clock selection signal 1-16 produced from the part 1-8 based on a program stored in a memory part 1-9 to a clock control part 1-7. In such a way, a high-speed clock is used in a normal state and a low-speed clock is used in a back-up mode with inhibition of the high-speed clock. This attains the reduction of power consumption.</p> |
